1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus is configured to store data and output stored data. The semiconductor memory apparatus receives serial type data, converts the serial type data into parallel type data, and stores the converted parallel type data. Also, the semiconductor memory apparatus converts stored parallel type data into serial type data and outputs the converted serial type data. The semiconductor memory apparatus converts parallel type data into serial type data according to an algorithm which converted the serial type data into the parallel type data.
When converting parallel type data into serial type data, a data sequence may be changed according to a specific address.
Referring to FIG. 1, a conventional semiconductor memory apparatus includes a data alignment control signal generation unit 10, a timing control unit 20, a data alignment unit 30, and a data output control signal generation unit 40.
The data alignment control signal generation unit 10 generates a data alignment control signal ctrl_r in response to a read pulse Read_p and a specific address Address.
The timing control unit 20 outputs the data alignment control signal ctrl_r as a timing control signal ctrl_t in response to a data output control signal PINCNT.
The data alignment unit 30 receives parallel data Data_p in response to the data output control signal PINCNT, converts the parallel data Data_p into serial data Data_s and outputs the converted serial data Data_s. When converting the parallel data Data_p into the serial data Data_s in response to the timing control signal ctrl_t, the data alignment unit 30 changes the sequence of the serial data Data_s.
The data output control signal generation unit 40 generates the data output control signal PINCNT in response to the read pulse Read_p.
Referring to FIG. 2, the timing control unit 20 includes a delay section 21 and a latch section 22.
The delay section 21 delays the data alignment control signal ctrl_r and outputs a delay control signal ctrl_d.
The latch section 22 latches the delay control signal ctrl_d in response to the data output control signal PINCNT and outputs the timing control signal ctrl_t.
Since the latch section 22 latches the delay control signal ctrl_d and outputs the timing control signal ctrl_t, if the delay time of the delay section 21 becomes shorter or longer than a preset delay time, the semiconductor memory apparatus is likely to output wrongly sequenced serial data.